Sample and hold circuit



Oct. 21, 1969 P, RODGERS 3,474,259

SAMPLE AND HOLD CIRCUIT Filed Dec. 17. 1965 I INVENTOR ROBERT P RODGER!A1 TURN EY United States Patent 3,474,259 SAMPLE AND I- OLD CIRCUITRobert P. Rodgers, Silver Spring, Md., assiguior to Singer- GeneralPrecision, Inc., a corporation of Delaware Filed Dec. 17, 1965, Ser. No.514,524 Int. Cl. H03f 3/68 US. Cl. 307238 6 Claims ABSTRACT OF THEDISCLOSURE In many situations Where a varying electrical signal is usedfor such things as monitoring the operation of several systems,providing input information for digital computers, high-speedcommunication and the like, multiplexing is used to save equipment. I nsuch systems, circuits which periodically sample the varying signals andhold the sample until the next sampling is made are important. Thisinvention is one such circuit. It comprises two pairs of differentiallyconnected amplifiers arranged so that one pair compensates for driftproduced in the other pair. A constant current power supply for one pairof differential amplifiers aids in stabilization. The output comprisespush-pull valves with means for limiting the quiescent current throughthem to improve the overall efliciency of the circuit. Field effecttransistors are used to provide large time constants Where needed.

This invention relates to sampling and holding circuits, and moreparticularly to circuits for sampling individual analog signals andholding them at the sampled level for a comparatively long interval oftime.

In many systems which use analog signals for their operation, oneprimary example being the various simulators for training persons in theoperation and control of aircraft, ships, and other vehicles andmachines, newer techniques involve performing the necessary operationson information by digital means. Since the information often originatesas analog information and is used as analog information, converters forconverting the information, between the analog and the digital systemsare needed. A single digital computer (actually, digital informationprocessor would be a better term) can manipulate information from manysources in very short time intervals. Analog information from trainingdevices does not usually vary at a rapid rate, but the instruments andother equipment controlled by the analog information may have lowinertia and virtually no storage facilities. This means that theinformation coming from the digital information processor and thedigital-to-analog converter must be directed to the proper instrumentand then stored at that level until the next time the same informationis available from the converter. To illustrate, in a radar simulatormany targets may be shown on the simulated radar screen. Each targetrequires its own information which locates its position on the screenand the manner in which it is moving. As conditions being simulatedchange, the information shown on the radar screen must also change.These changes occur at comparatively slow rates. Therefore, if a singledigital information processor and d-a converter is used to processinformation from the radar targets and also from many similar devices,the overall switching or multiplexing cycle may be quite long. A circuitfor each radar target must be provided between the d-a converter and theradar simulator to receive the information specific to each target atthe appropriate tmes and store that information iwth little change invalue until it again receives new information about the same target. Ofcourse, the above illustration is only thatan example of one type ofsystem in which the circuit of this invention may be used.

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i It is an object of this invention to provide a new and lmprovedcircuit for the sampling and holding of analog information.

It is another object of this invention to provide a new and improvedcircuit for use in analog systems for receiving and storing on commandanalog data at prescribed intervals.

It is a further object of this invention to provide a simple andinexpensive circuit module which is suitable for use in many differentsituations in which analog information is to be received and stored fora finite interval of time.

It is still another object of this invention to provide a solid statecircuit which is useable in a large number of situations, with little orno change, for the storage of electrical potentials for a prescribedinterval of time.

It is still a further object of this invention to provide a new andimproved circuit which is virtually free from potential drift with timeand which provides a very stable and inexpensive as Well as rugged meansfor sampling and storing electrical potentials.

Other objects and advantages of this invention will become more apparentas the following description proceeds, which description should beconsidered together with the accompanying drawings in which:

FIG. 1 is a block diagram of the sample and hold circuit of thisinvention, and

FIG. 2 is a schematic circuit diagram of the circuit of FIG. 1.

Referring now to the drawings in detail, the reference character 11designates a pair of signal input terminals, one of which is grounded.The ungrounded terminal 11 is connected to the input of an electronicsampling switch 12. A series of control pulses G for the sampling switch12 are applied to control input terminal 13, which is connected to agate 18. The output from the gate 18 controls the switching circuit 12to permit input signals A from the terminals 11 to be applied to oneside of a storage capacitor 14, the other side of which is grounded. Anamplifier 15 having a feedback path 16 has its signal input connectedacross the capacitor 14 and supplies an output signal 0 to a pair ofoutput terminals 17, one of which is grounded.

In operation, the analog signals, shown at A, are applied to the inputterminals 11. These analog signals may vary rapidly, but they usuallyvary at a relatively slow rate and they may be interrupted in nature.Thus, assuming that the input terminals 11 receive signals from a singledigital-to-analog converter which is, in turn, supplied from a singledigital information processor, the information output from the d-aconverter relates to a single analog device for only a short titheinterval. Then, the output of the d-a converter switches to informationwhich relates to another analog device. The digital processor and thed-a converter are multiplexed to handle the information from and to alarge number of analog devices in a given interval of time. The outputftom the d-a converter, which is being used here as an example of aninput device for the circuit of this invention, is directly connected tothe input terminals 11. Assuming that a large number of devices shown inFIG. 1 would be used in a single system, the input terminals 11 of allof them would be connected together and to the output from the d-aconverter. Electronic sampling switch 12 is normally opened but isclosed by the application of a control pulse from the gate 18. When acontrol pulse is applied to the control input terminal 13, the samplingswitch 12 closes to permit the electrical potential applied at that timeto the input terminals 11 to be applied acfoss the capacitor 14. Whenthe control pulse on terminal 13,decays, sampling switch 12 opens anddisconnects the capacitor 14 from the input. Thus, the amplifier 15 isleft as the single device which is connected across the capacitor 14.The input impedance of the amplifier must be of a value such that thecombination of the size of the capacitor 14, the amplifier 15 inputimpedance, and sampling switch 12 open circuit impedance will maintainthe charge on the capacitor 14 within the desired limits during the timewhen the sampling switch 12 is open. When sampling switch 12 closesagain, the capacitor 14 will charge to the potential then existing atthe input terminals 11. In addition to the input impedance requirementsof the amplifier 15, it must be virtually drift-free. A feedback path 16across the amplifier 15 is provided to set the closed loop gain of theamplifier precisely. At the output terminals 17, an amplified version ofthe input signal appears and is connected to the device which uses thatsignal.

One circuit which has been constructed to accomplish the resultsmentioned above for the system of FIG. 1 is shown in detail in FIG. 2.The same reference characters in both figures designate the sameelements. Input terminals 11, shown in FIG. 2 on the left, are connectedto ground and to the source electrode of a field effect transistor 21.The transistor 21 comprises the electronic sampling switch 12 of FIG. 1.The drain electrode of the transistor 21 is connected to one side of thestorage capacitor 14, the other side of which is connected to ground.The gate electrode of the transistor 21 is connected through astabilizing resistor 22 to the input terminal 11 and through a diode 23to the collector electrode of a transistor 18. The collector electrodeof the transistor 18 is connected through a load resistor 19 to a sourceof +12 volts, and the emitter electrode of the same transistor isconnected to 12 volts. The base electrode of the transistor 18 isconnected through a resistor 10 to the control input terminal 13 andthrough a resistor to a source 39 of 75 volts. The ungrounded side ofthe capacitor 14 is also connected to the gate electrode of a fieldeffect transistor 24 which comprises one side of a difierentiallyconnected amplifier, the other side of which is a similar field effecttransistor 25. The source electrodes of the two transistors 24 and 25are connected to opposite sides of a variable resistor 28 having asliding contact 29. The contact 29 is connected to the collectorelectrode of a transistor 31, the emitter electrode of which isconnected to a resistor and a Zener diode 33 to the positive side of asource 32 of 12 volts DC, the negtive side of which is connected througha resistor 34 to the other side of the diode 33. The base electrode ofthe transistor 36 is supplied with a constant positive potential fromthe source 32 through the slide contact of a potentiometer 36 and acrossthe Zener diode 33 which acts as a voltage regulator.

The drain electrodes of the two transistors 24 and 25 are connectedtogether through resistors 26 and 27, one side of resistor 26 beingconnected to the drain electrode of transistor 24, one side of theresistor 27 being connected to the drain electrode of the transistor 25,and the other sides of the resistors 26 and 27 being connected togetherand to the negative side of a source 40 of 20 volts DC. The output fromthe transistor 24 is taken from the one side of the resistor 26 and isapplied to the base electrode of a transistor 41, and the output fromtransistor 25 is taken from the one side of the resistor 27 and isapplied to the base electrode of a, transistor 42. Transistors 41 and 42form a differentially connected amplifier with the emitter electrodes ofeach of the two transistors connected to one side of each of tworesistors 43 and 44, respectively, the other sides of which areconnected together and through the potentiometer 36 and resistors 37 and38 to the positive terminal of the source 32. The collector electrode ofthe transistor 41 is connected to one side of a resistor 45, and thecollector electrode of the transistor 42 is connected through a Zenerdiode 46 to one side of a resistor 47. The other sides of the resistors45 and 47 are connected together and to the negative side of the source39 or 75 volts DC. The single output from the differentially connectedamplifier is taken from the junction of the Zener diode 46 and theresistor 47 and is applied to the input of a phase splitter whichcomprises transistor 51. The phase splitter 51 supplies the baseelectrodes of the transistors 52 and 53 which form a push-pull outputamplifier. The collector electrode of the transistor 51 is connectedthrough a load resistor 57 to the positive side of the source 39 of 75volts DC, and the emitter electrode of the same transistor is connectedthrough a Zener diode and a load resistor 54 to the negative side of thesource 39. The junction of the collector electrode of the transistor 51and the resistor 57 is connected across a diode 59 to the base electrodeof the transistor 53, and the junction of the diode and the resistor 54is connected to the base electrode of the transistor 52. The emitterelectrode of transistor 53 is connected to the collector electrode ofthe transistor 52, and to the ungrounded output terminal 17. The emitterelectrode of the transistor 52 is connected through a resistor and adiode 56 to the negative side of the source 39. In addition, twofeedback paths are provided from the ungrounded output terminal 17. Onefeedback path comprises a capacitor 61 and a resistor 62 and isconnected to the base electrode of the phase splitter transistor 51, andthe other path comprises a line 63 and a potentiometer 65 and isconnected to the gate electrode of the field effect transistor 25 in thefirst differential amplifier.

The circuit of FIG. 2 has been designed to accomplish the objectsoutlined above. Amplification in the over-all circuit may be in theorder of a gain of ten. The input potentials range between $5 volts DC.The output potentials will then range from 0 volts DC to about -50 voltsDC, or that potential which is required to establish full scale in thedevices driven by the circuit. Considering the example mentioned aboveof a system in which information is procesed in digital form and is thenconverted into analog form for application to the equipment whichutilizes it, a digital word may comprise 10 binary bits. Thus, the inputvariation in potential, :5 volts, is represented by 1024 units. Each bitrepresents about ten millivolts. Therefore, to maintain the accuracy ofthe system, there should be a drift in the system of less than fivemillivolts per switching cycle. The system is designed to hold a valuefor an interval of about one second. With slight modifications, thistime can easily be doubled. Therefore, during the one second that thevalue is held, it should change by less than five milli volts. Thestorage capacitor 14 may have, for example, a value of about 0.1microfarad. A field effect transistor 21 was chosen as the electronswitch because of the high off impedance which it exhibits and the factthat it has virtually no saturation voltage drop. However, when it isconducting, the transistor 21 has an impedance of about 1500 ohms. Thisdetermines the input charging rate. The time required to charge thecapacitor 14 of about 0.1 mf. through the transistor 21 to achieve acharge on capacitor of 0.9995 E is about eight times the time constantof capacitor 14 and transistor 21. This corresponds to a change in theoutput of about volts with an error of about 50 millivolts, or theequivalent of one-half bit on the input. Thus, with a capacitor of 0.110- f. and a charging impedance of 1500 ohms, the time constant is 10seconds, or 150 microseconds. Since it takes about eight to ten timesthis time to fully charge the capacitor 14, the minimum conductive timefor PET 21 should be in the order of 1500 microseconds. When thetransistor 21 is switched off; that is, nonconducting, the capacitor 14tends to discharge through the transistor 24, resistor 26, andtransistor 21. Field effect transistors maintain this discharge time ata maximum.

Once the capacitor 14 is charged with the input signal and the switchtransistor 21 stops conducting, the potential across the capacitor 14 isapplied to the gate electrode of the field effect transistor (FET) 24.The amount of current flowing through this transistor and through itsload resistor 26 depends primarily upon the effective conductance of thetransistor 24 which is controlled by the amplitude of the input signalapplied to the gate electrode. Transistor 31, through which the loadcurrent of FETs 24 and 25 must pass, is connected as a constant currentdevice with its base electrode connected to the fixed potentialdeveloped across a portion of the potentiometer 36 by the currentflowing from the 12 volt source 32. With the voltage of the baseelectrode relatively fixed, the current through the emitter-collectorpath of the transistor 31 does not change. This limits the amount ofcurrent supplied to the two FETs 24 and 25. When the voltage applied tothe gate electrode of the FET 24 increases, the current flowing throughthe FET 24 increases. This decreases the current available to flow fromthe transistor 31 through the PET 25. Thus, an effect on FET 24 producesan opposite effect upon FET 25. The voltage applied to the gateelectrode of PET 24 is determined by the charge on the storage capacitor14. The voltage applied to the gate electrode of the FET 25 isdetermined by the amplitude of the output signal at terminals 17. EachFET 24 and 25 has its own output. The output from FET 24 is applied tothe base electrode of transistor 41 and the output from FET 25 isapplied to the base electrode of the transistor 42. Thus, as the voltageacross the storage capacitor goes up, the voltage applied to the base oftransistor 42 goes up and the voltage applied to the base electrode ofthe transistor 41 goes down. Although the transistors 41 and 42 aredifferentially connected, an output is taken from only transistor 42across the resistor 47.

The differentially connected amplifier comprising transistors 41 and 42,the constant current device 31, the feedback path from the commonlyconnected emitter electrodes of the transistors 41 and 42 to the 12 voltsource 32, and the use of a Zener diode 33 across the 12 volt source 32,all contribute to reduce the drift in the amplifier, and in particular,to reduce the thermal drifts in the direct coupled amplifier stages. TheZener diode 33 is connected across the 12 volt source 32 and tends tocompensate for changes in the potential across the base to emitterterminals of transistor 31 due to temperature variations. The use of apotentiometer 36 to apply the potential to the base electrode of theconstant current device transistor 31 also permits variation in theapplied potential to help compensate for drift which occurs over a longinterval of time due to aging and the like. Using a common supply path,which incorporates series resistors 34 and 35 to supply power for theFETs 24 and 25 and resistors 36 and 38 to provide power for thetransistors 41 and 42, provides a negative feedback path which tends tocompensate for drift in the common mode. Further, using a pair oftransistors 41 and 42 differentially connected belt taking an outputfrom only one of the transistors 42 provides a drift corrector intransistor 41. The gain of the transistors 41 and 42 lies in thebase-collector path. The baseemitter path usually has a maximum gain ofunity. Thus, the feedback introduced by the variations in currentflowing through the transistor 41, due to changes in the charge incapacitor 14, does not nullify the gain of the transistor 42. Thefeedback is in the base-emitter path of the transistor 41 while theoutput is taken from the collector of the transistor 42.

The single output from the transistor 42 is taken across the loadresistor 47 and is applied to the base electrode of the transistor 51.Transistor 51 has two outputs, a high gain output from its collectorelectrode across load resistor 57 which is applied to the base electrodeof the transistor 53, and a low gain output taken from its emitteracross load resistor 54 and applied to the base electrode of thetransistor 52. The output from the transistor 53 is taken from itsemitter electrode and is, therefore, of approximately unity gain,whereas the output from transistor 53 is taken from its collector and ishigh gain. Thus, the over-all effect of the three transistors 51, 52 and53 is to provide a two-stage amplifier with a phase splitter and thesame over-all gain from both sides at the output at terminals 17. Thevoltage at the output terminals 17 is fed back through line 63, andpotentiometer to establish a potential on the gate electrode of thetransistor 25. Thus, when the system has stabilized with a fixedpotential across the storage capacitor 14, the potentiometers 65 and 28can be adjusted so that the current flowing through the FETs 24 and 25are equal. From this starting point, any change in the potential appliedto the gate electrode of PET 24 by the capacitor 14 will change the flowof current through the FET 24 and one side of the potentiometer 28.Since a limited and constant amount of current is available for thepotentiometer 28, when the current flow through FET 24 changes in onedirection, the current flow through the FET 25 must change in the otherdirection. The change in the current flowing through FET 25 is thentransferred to the base electrode of the transistor 42 where it isamplified and is then applied to the output circuit at the base oftransistor 51. Drift in the differentially connected circuit comprisingtransistors 41 and 42 affects both of the transistors in the samemanner. Therefore, when the current through the transistor 42 isincreased due to temperature changes, for example, the current flowingthrough the transistor 41 increases in the same manner and by the sameamount. This increase in current flow tends to reduce the potentialapplied across the transistors 41 and 42 due to the increased potentialdrops produced in resistors 37 and 38 and in potentiometer 36. Thus, thecompensation is twice that which it would be if a single amplifier stagewere used.

The above described device provides a rugged means for sampling avoltage which exists on a line for short intervals of time by openingthe input to the device on command. The sampled signal is used to chargethe capacitor 14 through the switch 12. The potential across thecapacitor 14 then controls the conduction through one side of adifferentially connected amplifier to produce an amplified output whichis proportional to the sampled potential. Drift is reduced by the use ofdifferentially connected amplifiers in which one side tends tocompensate for drift changes in the other and by means of feedbackcircuits. The use of field efliect transistors 24 and 25 provides a highimpedance device which reduces the amount of drain on the capacitor 14to the point where the loss of potential between sampling cycles iswithin the desired tolerances. The device of this invention alsoprovides gain sufiicient to operate other apparatus without theintervention of additional amplifiers. It is realized that the abovespecification may indicate to others in the art additional ways in whichthe principles of this invention may be used without departing from thespirit of this invention. It is, therefore, intended that this inventionbe limited only by the scope of the appended claims.

What is claimed is:

'1. A system for sampling an electrical signal and holding said signalfor future use, said system comprising:

(a) an electrical switch means having an information input, aninformation output and a control input;

(b) means for applying a signal to be sampled to said information inputand for applying control signals to said control input, said switchmeans being enabled to pass information from said information input tosaid information output under the control of said control signals;

(c) an information storage device connected to said information outputto receive information passing through said switch means, said storagedevice being of such a capacity that it is filled to the extent of theinput information available during the time that said control signalscause said switch means to pass information from its information inputto its information output so that the information stored in said storagedevice trully represents the information applied to said informationinput;

(d) a first differential amplifier comprising a first and a secondamplifying stage connected to provide at an output the differencebetween information applied to two inputs; means for connecting saidstorage device to the input of said first amplifying stage, said firstamplifying stage having an impedance such that the information stored insaid storage device does not appreciably leak through said firstamplifying stage during such times that said switch is disabled, andmeans for connecting the input to said second amplifying stage to theoutput of said system so that information appearing at said systemoutput is fed back and compared with the information in said storagedevice; and

(e) each of said first and second amplifying stages having a mainconductive path, means for connecting said main conductive paths of saidfirst and second amplifying stages together and in parallel; a source ofelectrical energy for energizing said first and second amplifyingstages; and a constant current device in series with said source ofelectrical energy and the parallel main conductive paths of said firstand second amplifying devices so that the total amount of currentsupplied to the parallel paths is relatively constant and is shared bysaid first and second paths.

2. The system defined in claim 1 further comprising:

(a) a second differentially connected amplifier;

(b) said second differentially connected amplifier comprising a thirdamplifying stage and a fourth amplifying stage, each of said third andfourth stages having an input, an output and a main conductive path;

(c) means for connecting the main conductive paths of said third andfourth stages together in parallel through similar resistors;

(d) means for applying said source of electrical energy to said commonlyconnected main conduction paths of said third and fourth stages;

(e) means for connecting the input of said third stage to the output ofsaid first stage, and means for connecting the input of said fourthstage to the output of said second stage;

(f) and means for taking an output from said fourth stage only.

3. The system defined in claim 2 further including:

(a) an output amplifier comprising a phase splitter stage, a firstoutput stage, and a second output stage;

(b) said phase splitter stage comprising a pair of output electrodes andan input electrode, means for connecting said input electrode to theoutput from said fourth stage;

() each of said first and second output stages comprising at least anoutput electrode and an input electrode;

(d) means for connecting one of said output electrodes of said phasesplitter to the input electrode of said first output stage, means forconnecting the other output electrode of said phase splitter to theinput electrode of said second output stage, and means for connectingthe output of said system to the output electrodes of said first andsecond output stages.

4. The system defined in claim 3 further including:

(a) a feedback path connected between the output of said system and theinput of said second stage;

(b) said feedback path including a variable impedance for adjusting theamount of energy applied from said system output to the gate electrodeof said second stage.

5. The system defined in claim 1 wherein said electronic switching meanscomprises a field effect transistor having a source electrode, a drainelectrode and a gate electrode, and means for biasing said gateelectrode to maintain said field effect transistor normallynonconducting whereby an electrical signal applied to said informationinput is transferred to said capacitor only upon command.

6. A sample and hold circuit comprising:

(a) an electronic switch comprising an input, an output and a controlterminal, means for connecting said input to a source of information tobe sampled, means for applying electrical control signals to saidcontrol terminal; said switch establishing a direct connection betweensaid input and said output under the control of the control signalsapplied to said control terminal;

(b) an information storage device connected to the output from saidswitch, said storage device having a storage capacity such that duringthe times that said switch is conductive said storage device is filledto the extent possible by the information available at the input;

(c) a first differential amplifier comprising a first amplifier stageand a second amplifier stage, each of said first and second stageshaving an input, an output, and a main conductive path, means forconnecting said storage device to the input of said first stage so thatthe information stored in said storage device controls the conductionthrough the main conductive path of said first stage;

(d) a constant current device, means for connecting together in parallelthe main conductive paths of said first and second stages, means forconnecting the parallel connected main conductive paths of said firstand second stages in series with said constant current device so thatthe output from said constant current device is divided between theconductive paths of said first and second stages;

(e) a second differential amplifier comprising third and fourthamplifier stages, each of said third and fourth stages including aninput, an output and a main conductive path, means for connecting theinput of said third stage to the output from said first stage; means forconnecting the input of said fourth stage to the output from said secondstage; means for connecting the main conductive paths of said third andfourth stages together and in parallel; and means for connecting theparallel arrangement of the third and fourth stages conductive paths tosaid source of electrical energy so that the current drawn by the saidthird and fourth conductive paths determines the potential applied tosaid constant current device from said source of energy;

(f) a phase splitter, means for connecting the input to said phasesplitter to the output from said fourth stage;

(g) a pair of output stages connected as a push-pull circuit with theinputs to the pair of output stages being taken from the two sides ofsaid phase splitter, means in said push-pull circuit to equalize thequiescent currents flowing therethrough, and means for taking the outputof the system from said pushpull circuit; and

(h) a feedback path connected from the output of the system to the inputto said second stage, whereby the information stored in said storagedevice determines the current flowing through said second stage, whichin turn determines the current flowing through said second stage, thecurrent flowing through said third and fourth stages further determiningthe current flowing through said constant current device whichdetermines the sum of the currents flowing through said first and secondstages,

said system comprising a closed loop system which 3,297,963 1/1967 Hal td 307346 X provides a stable amplification of a sampled input. 3,309,6183/ 1967 H i t 1, 330-69 References Cited NATHAN KAUFMAN, PrimaryExaminer UNITED STATES PATENTS 5 U.S.Cl.X.R. 3,158,759 11/1964 J p328-151 X 307-235, 246; 328-151; 330-30, 3s, 51, 69

3,181,013 4/1965 Harris 32858 X

